1. Field of Invention
The invention relates generally to data processing systems and specifically to the interrelation of functional units for the adaptation of processing resources to the requirements of input-output channels that service peripheral devices.
2. Description of the Prior Art
Reference is made to U.S. Pat. No. 3,815,099 entitled "Data Processing System" which is representative of the closest prior art.
In the typical data processor, the input and output data transfer between the system storage unit called the memory and an external data source or terminal called a peripheral device interferes with the operation of the unit called the processor. The interference takes many forms. In some cases, the processor executes an instruction to control the transfer and usually remains in the transfer path. The processor may also be able to transfer control to the peripheral device for a direct memory access, but the processor still has to perform some preliminary handoff operations and often cycle synchronizing and terminating operations as well. Or, on some common-bus arrangements, the processor has to process the interrupts, granting or withholding bus access. In any of these cases, the data transfer interrupts data processing. And, since the average peripheral device is slow compared even to the speed of a minicomputer, the interruption significantly reduces processing efficiency. Since the typical data processing system has only a single processor, the inefficiency of the processor seriously degrades system performance. Although some systems have more than one processor, the additional processors are usually dedicated to special functions or assigned to execute separate programs. Such processors cannot achieve the same level of performance as can similar processors in a multiprocessing and multitasking configuration.
It is therefore an object of the present invention to provide a data processing system with a multiprocessing and multitasking capability that enables several processors to cooperate in executing instructions from the same program in whatever order the processors are available.
It is another object of the invention to provide an efficient system configuration that interconnects processors, memory units, and a variety of input-output channels via a relatively high-speed time-division multiplex bus with a bus controller that reduces the interference between data transfer and data processing.
It is a further object of the invention to provide a system configuration in which the main memory serves as a common buffer between all processors and a variety of input-output channels.
It is an additional object of the invention to provide a system that can be optimally tailored to accommodate almost any combination of processing and input-output requirements merely by the selection of the appropriate number and position of suitable modular units.
Other objects and advantages of the invention will be obvious from the detailed description of a preferred embodiment given herein below.